(a) Field of the Invention
The present invention relates to a process for forming multilevel interconnection (wiring) structure for a semiconductor device and, more particularly, to a process for forming a multilevel interconnection structure having a copper layer for a lower electric resistance and a higher layout density.
(b) Description of the Related Art
In a conventional wiring process employed in fabrication of a semiconductor device, an aluminum or aluminum alloy layer is subjected to photolithographic and etching steps so as to form first level interconnects. Then, an interlevel dielectric film is deposited on the first level interconnects, followed by flattening thereof. Subsequently, a via hole is formed in the interlevel dielectric film and is filled with a tungsten plug. An aluminum or aluminum alloy layer is then deposited on the interlevel dielectric film and is subjected to photolithographic and etching steps so as to form second level interconnects.
As the number of interconnect levels of a multilevel interconnection structure increases, the process for fabrication of semiconductor devices becomes complex due to an increase in the number of photolithographic and etching steps. Also, as the pitch of interconnects becomes finer, the coverage of the interlevel dielectric film tends to become incomplete to form voids therein.
In a current generation of semiconductor devices having a line width of 0.18 .mu.m to 0.20 .mu.m, the pitch of interconnects is reduced to increase the parasitic capacitance between the interconnects, whereby the performance of the semiconductor devices tend to be deteriorated due to a large RC time constant. One solution for this problem is provision of copper interconnects having a lower electric resistance than aluminum or aluminum alloy interconnects. However, the difficulty of etching control in copper property prevents an ordinary etching process, such as a combination of deposition and subsequent etching steps, from being employed.
A damascene process is of particular interest as a process for forming a multilevel copper interconnection structure. Formation of the multilevel copper interconnection structure by the damascene process will next be described with reference to FIGS. 1A-1I.
Referring to FIG. 1A, a first SiO.sub.2 film, such as BPSG (borophospho-silicate glass) film 14 is formed on a silicon substrate 12. A via hole (not shown) is formed in the first SiO.sub.2 film 14 so as to expose a portion of diffused region (source/drain region) of the silicon substrate 12. A conductive plug (not shown), such as a tungsten plug, is then formed in the via hole for connection of the diffused regions with overlying interconnects.
Subsequently, as shown in FIG. 1B, a second SiO.sub.2 film 16 is formed on the first SiO.sub.2 film 14 by a plasma CVD process. The plasma CVD process uses, for example, silane (SiH.sub.4 and oxygen (O.sub.2) as reactive gases.
Next, as shown in FIG. IC, a photoresist film 18 is formed on the second SiO.sub.2 film 16. The photoresist film 18 is subjected to patterning by photolithographic and etching steps to be formed into a patterned mask 18 having a pattern thereon for interconnects. Subsequently, the second SiO.sub.2 film 16 is etched using the patterned mask 18 as an etching mask, thereby forming a wiring trench 20, which exposes at the bottom thereof the conductive plug (not shown) formed in the SiO.sub.2 film 14.
Then, the mask 18 is removed by oxygen plasma ashing using a plasma ashing system, such as having parallel-plate electrodes. An RF voltage is applied for the ashing between the top electrode and the bottom electrode of the plasma ashing system.
Subsequently, as shown in FIG. 1D, a TiN film 22 serving as a barrier layer is blanket-deposited on the wafer. Further, a copper layer 24 is deposited on the TiN film 22 to fill the wiring trench 20.
Then, the copper layer 24 and the TiN film 22 are subjected to a chemical-mechanical polishing (CMP) step until the top of the SiO.sub.2 film 16 is exposed, thereby forming first level copper interconnects 24 in the trench as shown in FIG. 1E. The first level copper interconnects 24 are in electrical contact with the conductive plug (not shown) at the bottom thereof, are exposed at the top surface of the copper interconnects, and are embedded in the SiO.sub.2 film 14.
Further, a third SiO.sub.2 film, such as BPSG film, 26 is formed on the second SiO.sub.2 film 16 and the first level interconnects 24. A photoresist film 28 is then formed on the second SiO.sub.2 film 26. The photoresist film 28 is subjected to patterning so as to be formed into a patterned mask 28. Next, as shown in FIG. 1F, the third SiO.sub.2 film 26 is selectively etched by a plasma etching process using the patterned mask 28 as an etching mask, thereby forming a via hole 30 which exposes the top of the first level copper interconnects 24.
Subsequently, the patterned mask 28 is removed by oxygen plasma ashing under specified ashing conditions similar to those employed for the patterned mask 18. During the oxygen plasma ashing process, the first level copper interconnects 24 are exposed to an oxygen plasma ambient through the via hole 30.
Then, as shown in FIG. 1G, a TiN film 32 serving as a barrier layer is blanket-deposited on the wafer, followed by deposition of a tungsten layer 34 on the TiN film 32.
The TiN film 32 and the tungsten layer 34 are then subjected to a CMP process until the top of the third SiO.sub.2 film 26 is exposed, thereby leaving a tungsten plug 34 filling the via hole 30 as shown in FIG. 1H.
Further, a fourth SiO.sub.2 film 38 is formed on the third SiO.sub.2 film 26 by a plasma CVD process. As in the case of the first level copper interconnects 24, a wiring trench is formed in the fourth SiO.sub.2 film 38. A TiN film 40 is formed on the fourth SiO.sub.2 film 38, followed by deposition of another copper layer 42 on the TiN film 40. The TiN film 40 and the copper layer 42 are subjected to a CMP process so as to leave second level copper interconnects 42 in the trench. In order to remove the etching mask after formation of the wiring trench, oxygen plasma ashing is performed under specific ashing conditions similar to those employed for removal of the masks 18 and 28. During the oxygen plasma ashing process, the tungsten plug 34 is exposed to an oxygen plasma ambient through the wiring trench in the fourth SiO.sub.2 film 38.
The above-described damascene process for forming a multilevel copper interconnection structure involves an unavoidable increase in the electric resistance of the first and the second level copper interconnects and an increase in the contact resistance between the interconnects and the tungsten plug.
Such an increase in electric resistance or contact resistance restricts the implementation of a finer pitch of the interconnects and a larger number of levels in the multilevel interconnection structure, thereby hindering the implementation of a semiconductor device of higher integration.
The above problem also arises in a conventional ordinary process including the steps of: forming a copper layer; subjecting the copper layer to patterning to form copper interconnects; embedding the copper interconnects with an interlevel dielectric film; transferring a via-hole pattern onto the interlevel dielectric film; and forming the via holes.